Timing System Structure
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- Category: Timing System
- Last Updated on Wednesday, 16 March 2011 08:28
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The Timing System consists of an Event Generator (EVG) which converts timing events and signals to an optical signal distributed through Fan-Out Units to an array of Event Receivers (EVRs). The Event Receivers decode the optical signal and produce hardware and software output signals based on the timing events.
By combining an event driven timing system with direct distribution of a set of signal the system achieves great flexibility. The system utilises 256 event codes and allows distribution of eight simultaneous signals which do not interfere with events. Events and the distributed bus signals are sampled with the event clock rate which e.g. for the VME products has to be in range 50 MHz to 125 MHz. The event clock may be generated on board the EVG or better divided from an externally supplied clock reference, the RF signal.
Event Receivers use a PLL circuit to lock precisely to the event clock of the Event Generator, so the hardware outputs are phase locked to the event clock and to the RF signal if applicable.