Setting the Delay on UNIV-LVPECL-DLY and UNIV-TTL-DLYModule

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Category: Universal I/O Modules

Last Updated on Tuesday, 08 June 2021 11:47

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The UNIV-LVPECL-DLY and UNIV-TTL-DLY module is controlled through four general purpose I/O pins available only on the two front panel slots of the VME-EVRs and the cPCI-EVR. The I/O pins are listed in the following table.

The Output Disable signal drives the /EN signal of the delay chips which tri-states the output of the delay chip when high. Note that there are 130 ohm bias/termination resistors to ground on both of the signals of the LVPECL differential pair.

On the module there is a 24 bit serial shift register that provides the 10 bit delay value to both output channels. The delay value consists of bits DA0 to DA9 for one channel and DB0 to DB9 for the other channel. DA0 and DB0 are the least significant bits. In addition to the delay values there is a parallel latch enable bit for both channels. When logic low LENA and LENB pass the data through, when high the delay values are latched.

The diagram below shows how the bits are shifted in on the rising edge of SCLK. A rising edge on LCLK transfers the data from the shift register to the actual delay chips which are two Micrel SY100EP196.

In the EVR (old VME register mapping) the Universal I/O module GPIO pins are controlled through a single 32 bit register that provides access to the GPIO pins of two Universal I/O slots.

A GPIO pin is configured as output when the DIR bit is set '1'.

The newer Modular register map firmware versions have separate 32 bit registers for IN, OUT and DIR.

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