Setting the Delay on UNIV-LVPECL-DLY Module

The UNIV-LVPECL-DLY module is controlled through four general purpose I/O pins available only on the two front panel slots of the VME-EVRs and the cPCI-EVR. The I/O pins are listed in the following table.

GPIO
Pin Name
Pin Function
GPIO0 DIN Serial Data
GPIO1 SCLK Serial Clock
GPIO2 LCLK Transfer Latch Clock
GPIO3 DIS Output Disable

The Output Disable signal drives the /EN signal of the delay chips which tri-states the output of the delay chip when high. Note that there are 130 ohm bias/termination resistors to ground on both of the signals of the LVPECL differential pair.

On the module there is a 24 bit serial shift register that provides the 10 bit delay value to both output channels. The delay value consists of bits DA0 to DA9 for one channel and DB0 to DB9 for the other channel. DA0 and DB0 are the least significant bits. In addition to the delay values there is a parallel latch enable bit for both channels. When logic low LENA and LENB pass the data through, when high the delay values are latched.

The diagram below shows how the bits are shifted in on the rising edge of SCLK. A rising edge on LCLK transfers the data from the shift register to the actual delay chips which are two Micrel SY100EP196.

Bit Bang Pattern for UNIV-LVPECL-DLY Delay Adjustment

In the EVR (old VME register mapping) the Universal I/O module GPIO pins are controlled through a single 32 bit register that provides access to the GPIO pins of two Universal I/O slots.

Bit Name Slot Function
0 (LSB) GPIN0 0 Input state of slot 0 pin GPIO0
1 GPIN1 0 Input state of slot 0 pin GPIO1
2 GPIN2 0 Input state of slot 0 pin GPIO2
3 GPIN3 0 Input state of slot 0 pin GPIO3
4 GPIN4 1 Input state of slot 1 pin GPIO0
5 GPIN5 1 Input state of slot 1 pin GPIO1
6 GPIN6 1 Input state of slot 1 pin GPIO2
7 GPIN7 1 Input state of slot 1 pin GPIO3
8 GPOUT0 0 Output state of slot 0 pin GPIO0
9 GPOUT1 0 Output state of slot 0 pin GPIO1
10 GPOUT2 0 Output state of slot 0 pin GPIO2
11 GPOUT3 0 Output state of slot 0 pin GPIO3
12 GPOUT4 1 Output state of slot 1 pin GPIO0
13 GPOUT5 1 Output state of slot 1 pin GPIO1
14 GPOUT6 1 Output state of slot 1 pin GPIO2
15 GPOUT7 1 Output state of slot 1 pin GPIO3
16 GPDIR0 0 Direction of slot 0 pin GPIO0
17 GPDIR1 0 Direction of slot 0 pin GPIO1
18 GPDIR2 0 Direction of slot 0 pin GPIO2
19 GPDIR3 0 Direction of slot 0 pin GPIO3
20 GPDIR4 1 Direction of slot 1 pin GPIO0
21 GPDIR5 1 Direction of slot 1 pin GPIO1
22 GPDIR6 1 Direction of slot 1 pin GPIO2
23 GPDIR7 1 Direction of slot 1 pin GPIO3

A GPIO pin is configured as output when the DIR bit is set '1'.


The newer Modular register map firmware versions have separate 32 bit registers for IN, OUT and DIR.